SH7080 Datasheet, PDF (999/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.7 Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 18.22 shows the timing of the bit synchronous circuit and table 18.6 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
SCL
Monitor SCL pin level
V_IH
Monitor SCL pin level
Internal SCL
Figure 18.22 The Timing of the Bit Synchronous Circuit
Rev. 3.00 May 17, 2007 Page 941 of 1582
REJ09B0181-0300