SH7080 Datasheet, PDF (1330/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Flash Memory
23.6.2 Software Protection
Software protection is set up in any of three ways: by disabling the downloading of on-chip
programs for programming and erasing, by means of a key code, and by the RAM emulation
register (RAMER).
Table 23.10 Software Protection
Function to be Protected
Item
Description
Download
Programming/
Erasure
Protection by the Clearing the SCO bit in FCCS disables √
√
SCO bit
downloading of the programming/erasing
program, thus making the LSI enter a
programming/erasing-protected state.
Protection by FKEY Downloading and programming/erasing √
√
are disabled unless the required key code
is written in FKEY. Different key codes are
used for downloading and for
programming/erasing.
Emulation protection Setting the RAMS bit in RAMER to 1
√
√
makes the LSI enter a
programming/erasing-protected state.
23.6.3 Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the
form of the microcomputer getting out of control during programming/erasing of the flash
memory or operations that are not in accordance with the established procedures for
programming/erasing. Aborting programming or erasure in such cases prevents damage to the
flash memory due to excessive programming or erasing.
If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER
bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or
erasure.
Rev. 3.00 May 17, 2007 Page 1272 of 1582
REJ09B0181-0300