SH7080 Datasheet, PDF (885/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value
R/W Description
2
SCKDT Undefined R/W SCK Port Data
Controls the SCK pin in combination with the SCKIO bit
in this register, the C/A bit in SCSMR, and bits CKE1
and CKE0 in SCSCR. Select the SCK pin function in
the PFC (pin function controller) beforehand.
C/A CKE1 CKE0 SCKIO SCKDT: SCK pin state
00
0
0
×:
Setting prohibited
00
0
1
0:
00
0
1
1:
00
1
×
×:
01
0
×
×:
(initial state)
Low level output
High level output
Internal clock output
according to serial core
logic
External clock input to
01
1
×
×:
10
0
×
×:
serial core logic
Setting prohibited
Internal clock output
10
1
×
×:
according to serial core
logic
Internal clock output
11
0
×
×:
according to serial core
logic
External clock input to
11
1
×
×:
serial core logic
Setting prohibited
Note: ×: Don't care
1
SPBIO 0
R/W Serial Port Break Output Control
Controls the TXD pin in combination with the SPBDT bit
in this register and the TE bit in SCSCR.
0
SPBDT Undefined R/W Serial Port Break Data
Controls the TXD pin in combination with the SPBIO bit
in this register and the TE bit in SCSCR. Select the
TXD pin function in the PFC (pin function controller)
beforehand.
TE SPBIO SPBDT: TXD pin state
00
×:
Setting prohibited (initial state)
01
0:
Low level output
01
1:
High level output
0×
×:
Transmit data output according
to serial core logic
Note: ×: Don't care
Rev. 3.00 May 17, 2007 Page 827 of 1582
REJ09B0181-0300