SH7080 Datasheet, PDF (890/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
(1) Transmit/Receive Formats
Table 16.15 lists the eight communication formats that can be selected in asynchronous mode. The
format is selected by settings in the serial mode register (SCSMR).
Table 16.15 Serial Communication Formats (Asynchronous Mode)
SCSMR Bits
CHR PE STOP 1
Serial Transmit/Receive Format and Frame Length
2 3 4 5 6 7 8 9 10 11 12
0 0 0 START
8-bit data
STOP
0 0 1 START
8-bit data
STOP STOP
0 1 0 START
8-bit data
P STOP
0 1 1 START
8-bit data
P STOP STOP
1 0 0 START
7-bit data
STOP
1 0 1 START
7-bit data
STOP STOP
1 1 0 START
7-bit data
P STOP
1 1 1 START
[Legend]
START: Start bit
STOP: Stop bit
P:
Parity bit
7-bit data
P STOP STOP
(2) Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the
C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control
register (SCSCR). For selection of the SCIF clock source, see table 16.14.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to 16 times the desired bit rate.
Rev. 3.00 May 17, 2007 Page 832 of 1582
REJ09B0181-0300