SH7080 Datasheet, PDF (164/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
UBC
WDT
DMAC
CMT
MTU2
A/D
SCIF
SCI
MTU2S
I²C2
POE
SSU
BSC
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
DTC
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTCERA to
DTCERE
DMAC
ICR0
IRQCR
IRQSR
IPR
IPRA to IPRF,
IPRH to IPRM
CHCR[11:8]
Module bus
Bus
interface
[Legend]
UBC: User break controller
WDT: Watchdog timer
CMT: Compare match timer
SCIF: Serial communication interface with FIFO
SCI: Serial communication interface
DMAC: Direct memory access controller
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2S
A/D:
I²C2:
A/D converter
I²C bus interface 2
POE: Port output enable
SSU: Synchronous serial communication unit
DTC: Data transfer controller
INTC
BSC:
Bus state controller
ICR0:
Interrupt control register 0
IRQCR:
IRQ control register
IRQSR:
IRQ status register
IPRA to IPRF,
IPRH to IPRM:
Interrupt priority registers A to F and H to M
SR:
Status register
CHCR:
DMA channel control register
DTCERA to DTCERE: DTC enable registers A to E
Figure 6.1 Block Diagram of INTC
Rev. 3.00 May 17, 2007 Page 106 of 1582
REJ09B0181-0300