SH7080 Datasheet, PDF (997/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.5 I²C2 Interrupt Sources
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 18.4 shows the
contents of each interrupt request.
Table 18.4 Interrupt Requests
Interrupt Request
Abbreviation Interrupt Condition
I²C Mode
Clock
Synchronous DTC
Mode
Activation
Transmit data Empty IITXI
(TDRE=1) ^• (TIE=1) √
√
√
Transmit end
IITEI
(TEND=1) ^• (TEIE=1) √
√
×
Receive data full
IIRXI
(RDRF=1) ^• (RIE=1) √
√
√
STOP recognition IISTPI
(STOP=1) ^• (STIE=1) √
×
×
NACK receive
IINAKI
{(NACKF=1)+(AL=1)} ^• √
×
×
Arbitration lost/
(NAKIE=1)
√
√
×
overrun error
When the interrupt condition described in table 18.4 is 1, the CPU executes an interrupt exception
handling. Interrupt sources should be cleared in the exception handling. The TDRE and TEND
bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is
automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time
when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an
excessive data of one byte may be transmitted. The TDRE, TEND, and RDRF bits are
automatically cleared while the specified number of transfers by the DTC is in progress; however,
the TDRE, TEND, and RDRF bits are not cleared automatically when the transfer is complete.
Rev. 3.00 May 17, 2007 Page 939 of 1582
REJ09B0181-0300