SH7080 Datasheet, PDF (334/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
6
CMIE
0
R/W Compare Match Interrupt Enable
Enables or disables CMF interrupt requests when the
CMF bit in RTCSR is set to 1.
0: Disables CMF interrupt requests.
1: Enables CMF interrupt requests.
5 to 3 CKS[2:0] 000
R/W Clock Select
Select the clock input to count-up the refresh timer
counter (RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
2 to 0 RRC[2:0] 000
R/W Refresh Count
Specify the number of continuous refresh cycles, when
the refresh request occurs after the coincidence of the
values of the refresh timer counter (RTCNT) and the
refresh time constant register (RTCOR). These bits can
make the period of occurrence of refresh long.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
Rev. 3.00 May 17, 2007 Page 276 of 1582
REJ09B0181-0300