SH7080 Datasheet, PDF (52/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Table 11.59
TICCR Setting and Input Capture Input Pins ................................................... 528
PWM Output Registers and Output Pins .......................................................... 533
Phase Counting Mode Clock Input Pins ........................................................... 537
Up/Down-Count Conditions in Phase Counting Mode 1.................................. 538
Up/Down-Count Conditions in Phase Counting Mode 2.................................. 539
Up/Down-Count Conditions in Phase Counting Mode 3.................................. 540
Up/Down-Count Conditions in Phase Counting Mode 4.................................. 541
Output Pins for Reset-Synchronized PWM Mode ............................................ 544
Register Settings for Reset-Synchronized PWM Mode.................................... 544
Output Pins for Complementary PWM Mode .................................................. 547
Register Settings for Complementary PWM Mode .......................................... 548
Registers and Counters Requiring Initialization ............................................... 554
MTU2 Interrupts............................................................................................... 606
Interrupt Sources and A/D Converter Start Request Signals ............................ 609
Mode Transition Combinations ........................................................................ 640
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Table 12.1 MTU2S Functions ................................................................................................ 672
Table 12.2 Pin Configuration.................................................................................................. 675
Table 12.3 Register Configuration.......................................................................................... 676
Section 13 Port Output Enable (POE)
Table 13.1 Pin Configuration.................................................................................................. 681
Table 13.2 Pin Combinations.................................................................................................. 682
Table 13.3 Register Configuration.......................................................................................... 683
Table 13.4 Target Pins and Conditions for High-Impedance Control .................................... 705
Table 13.5 Interrupt Sources and Conditions.......................................................................... 710
Section 14 Watchdog Timer (WDT)
Table 14.1 WDT Pin Configuration........................................................................................ 715
Table 14.2 Register Configuration.......................................................................................... 716
Section 15 Serial Communication Interface (SCI)
Table 15.1 Pin Configuration.................................................................................................. 725
Table 15.2 Register Configuration.......................................................................................... 726
Table 15.3 SCSMR Settings ................................................................................................... 744
Table 15.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) ................................. 745
Table 15.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2) ................................. 746
Table 15.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3) ................................. 747
Table 15.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1) ......................... 748
Table 15.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2) ......................... 749
Table 15.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3) ......................... 750
Rev. 3.00 May 17, 2007 Page lii of Iviii