SH7080 Datasheet, PDF (354/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.4 CSn Assert Period Extension
The number of cycles from CSn assertion to RD, WRxx assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from RD, WRxx negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles, RD and WRxx are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
Th
T1
T2
Tf
CK
A29 to A0
CSn
RDWR
Read
RD
D31 to D0
Write
WRxx
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.10 CSn Assert Period Extension
Rev. 3.00 May 17, 2007 Page 296 of 1582
REJ09B0181-0300