SH7080 Datasheet, PDF (899/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Serial
data
Start
1 bit
Data
Parity Stop Start
bit bit bit
Data Parity Stop
bit bit
1
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1
Idle state
(mark state)
RDF
FER
RXIF interrupt
request
One frame
Data read and RDF flag
read as 1 then cleared to
0 by RXIF interrupt handler
ERIF interrupt request
generated by receive
error
Figure 16.9 Example of SCIF Receive Operation
(8-Bit Data, Parity, One Stop Bit)
5. When modem control is enabled, the RTS signal is output depending on the empty status of
SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that the
SCFRDR is full and no extra data can be received.
Figure 16.10 shows an example of the operation when modem control is used.
Serial data
RXD
Start
bit
0 D0 D1 D2
Parity Stop
bit bit
D7 0/1 1
Start
bit
0 D0 D1
D7 0/1
RTS
Figure 16.10 Example of Operation Using Modem Control (RTS)
Rev. 3.00 May 17, 2007 Page 841 of 1582
REJ09B0181-0300