SH7080 Datasheet, PDF (297/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Address
Area
Memory Type
Capacity
Bus
Width
H'FFFF4000 to On-chip RAM
H'FFFFBFFF
32 Kbytes 32 bits
H'FFFFC000 to On-chip peripheral
H'FFFFFFFF modules
16 Kbytes
8 or 16
bits
Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation
cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on-
chip peripheral modules can be accessed; the other areas cannot be accessed.
* The bus width is selected by the register setting.
Table 9.15 Address Map: SH7086 in On-Chip ROM-Disabled Mode
Address
H'00000000 to
H'03FFFFFF
Area
CS0 space
H'04000000 to CS1 space
H'07FFFFFF
H'08000000 to CS2 space
H'0BFFFFFF
H'0C000000 to CS3 space
H'0FFFFFFF
H'10000000 to CS4 space
H'13FFFFFF
H'14000000 to CS5 space
H'17FFFFFF
Memory Type
Normal space
SRAM with byte selection
Burst ROM (asynchronous)
Burst ROM (synchronous)
Normal space
SRAM with byte selection
Normal space
SRAM with byte selection
SDRAM
Normal space
SRAM with byte selection
SDRAM
Normal space
SRAM with byte selection
Burst ROM (asynchronous)
Normal space
SRAM with byte selection
PCMCIA
MPX-I/O
Capacity
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
64 Mbytes
Bus
Width
16 or 32
bits*¹
8, 16, or
32 bits*²
8, 16, or
32 bits*²
8, 16, or
32 bits*²
8, 16, or
32 bits*²
8, 16, or
32 bits*²
Rev. 3.00 May 17, 2007 Page 239 of 1582
REJ09B0181-0300