SH7080 Datasheet, PDF (1009/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Initial
Bit Bit Name Value
10

0
9
CONADF 0
8
STC
0
7, 6 CKSL[1:0] 00
Section 19 A/D Converter (ADC)
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W ADF Control
Controls setting of the ADF bit in 2-channel scan
mode. The setting of this bit is valid only when
triggering of A/D conversion is enabled (TRGE = 1) in
2-channel scan mode. The setting of this bit is ignored
in single mode, 4-channel scan mode, or 8-channel
scan mode.
0: The ADF bit is set when A/D conversion started by
the group 0 trigger or group 1 trigger has finished.
1: The ADF bit is set when A/D conversion started by
the group 0 trigger and A/D conversion started by
the group 1 trigger have both finished. Note that the
triggering order has no affect.
When changing the operating mode, first clear the
ADST bit to 0.
R/W State Control
Sets the A/D conversion time in combination with the
CKSL1 and CKSL0 bits.
0: 50 states
1: 64 states
When changing the A/D conversion time, first clear the
ADST bit to 0.
R/W Clock Select 1 and 0
Select the A/D conversion time.
00: Pφ/4
01: Pφ/3
10: Pφ/2
11: Pφ
When changing the A/D conversion time, first clear the
ADST bit to 0.
CKSL[1:0] = B'11 can be set while Pφ ≤ 25 [MHz].
Rev. 3.00 May 17, 2007 Page 951 of 1582
REJ09B0181-0300