SH7080 Datasheet, PDF (782/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Serial Communication Interface (SCI)
• Choice of LSB-first or MSB-first data transfer (except for 7-bit data in asynchronous mode)
• Four types of interrupts: There are four interrupt sources, transmit-data-empty, transmit end,
receive-data-full, and receive error interrupts, and each interrupt can be requested
independently. The data transfer controller (DTC) or the direct memory access controller
(DMAC) can be activated by the transmit-data-empty interrupt or receive-data-full interrupt to
transfer data.
• Module standby mode can be set
Figure 15.1 shows a block diagram of the SCI.
RXD
TXD
SCK
SCRDR
SCRSR
Module data bus
SCTDR
SCSSR
SCBRR
SCSCR
SCTSR
SCSMR
SCSPTR
SCSDCR
Transmission/reception
control
Baud rate
generator
Parity generation
Parity check
Clock
External clock
SCI
[Legend]
SCRSR: Receive shift register
SCRDR: Receive data register
SCTSR: Transmit shift register
SCTDR:
SCSMR:
SCSCR:
SCSSR:
Transmit data register
Serial mode register
Serial control register
Serial status register
SCBRR: Bit rate register
SCSPTR: Serial port register
SCSDCR: Serial direction control register
Figure 15.1 Block Diagram of SCI
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TEI
TXI
RXI
ERI
Rev. 3.00 May 17, 2007 Page 724 of 1582
REJ09B0181-0300