SH7080 Datasheet, PDF (1623/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
Figure 22.14 Port E (SH7086) 1202 Deleted
PE2 (I/O)/DREQ1 (input)/TIOC0C (I/O)/
AUDRST (input) *
PE1 (I/O)/TEND0 (output)/TIOC0B (I/O)/
AUDMD (input) *
23.1 Features
1216 Amended
• Operating frequency for programming/erasing
The operating frequency for programming/erasing is
a maximum of 40 MHz (Pφ).
23.4.3 Programming/Erasing
1244, Amended
Interface Parameters
1245 _{Bit Bit Name Description}
(3) Programming Execution
(3.3) Flash pass/fail result
parameter (FPFR: general register
R0 of CPU)
4 FK
Flash Key Register Error Detect
Returns the check result of the value of FKEY
before the start of the programming processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than
H'5A)
(4) Erasure Execution
1249 Amended
(4.2) Flash pass/fail result
parameter (FPFR: general register
R0 of CPU)
Bit Bit Name Description
4 FK
Flash Key Register Error Detect
Returns the check result of FKEY value before
start of the erasing processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than
H'5A)
23.5.2 User Program Mode
1258 Added
(2) Programming Procedure in User Program Mode
…. Specify 1/4 (initial value) as the frequency division
ratios of an internal clock (Iφ), a bus clock (Bφ), and a
peripheral clock (Pφ) through the frequency control
register (FRQCR).
After the programming/erasing program has been
downloaded and the SCO bit is cleared to 0, the setting
of the frequency control register (FRQCR) can be
changed to the desired value.
Rev. 3.00 May 17, 2007 Page 1565 of 1582
REJ09B0181-0300