SH7080 Datasheet, PDF (440/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Iφ
L bus
Bφ (CK)
I bus
External bus
External access
(1 + n) × Iφ
This access period is
prolonged by a period of m.
(3 + m) × Bφ
In this example, m = 0.
For the numbers of cycles by which
m prolongs the access process,
see section 9.4, Register Descriptions.
1 × Iφ
Figure 9.55 Timing of Read Access with Condition Iφ:Bφ = 4:1 and
External Bus Width ≥ Data Width
For access by the DMAC or the DTC, the access cycles are obtained by subtracting the cycles of
Iφ required for L-bus access from the access cycles required for access by the CPU.
Rev. 3.00 May 17, 2007 Page 382 of 1582
REJ09B0181-0300