SH7080 Datasheet, PDF (1604/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
Table 8.11 DTC Bus Release
Timing
207 Amended
Bus Function Extending Register (BSCEHR) Setting
Setting
DTLOCK CSSTP1 CSSTP2 CSSTP3 DTBST
Setting 1*⁴ 1
0
*³
1
0
Setting 2*³ 0
0
0
*³
0
Setting 3 0
1
*³
*³
0
Setting 4*² 0
1
*³
*³
1
Setting 5 1
1
*³
1
0
Notes: 1. The bus mastership is only released for the
external space access request from the CPU
after a vector read.
3. Don't care.
4. Set the CSSTP3 bit to 1 when selecting
setting 1.
8.9.11 Operation when a DTC
Activation Request is Cancelled
While in Progress
215 Added
9.3.1 Area Division
222 Added
CS0 is asserted during area 0 access. In access to
SDRAM connected to areas 2 and 3, signals such as
RASx, CASx, RD/WR, and DQMxx will be asserted.
Furthermore, when the PCMCIA interface is selected in
areas 5 and 6, CE1A, CE1B, CE2A, and CE2B as well
as CS5 and CS6 are asserted, according to the bytes to
be accessed.
Table 9.2 Address Map: SH7083
(256-Kbyte Flash Memory
Version) in On-Chip ROM-
Enabled Mode
222,
223
Amended
Address
H'0C000000 to H'0DFFFFFF
H'0E000000 to H'1BFFFFFF
Area
Capacity
CS3 space 32 Mbytes
Reserved
H'1C000000 to H'1DFFFFFF CS7 space 32 Mbytes
H'1E000000 to H'FFF7FFFF Reserved
Rev. 3.00 May 17, 2007 Page 1546 of 1582
REJ09B0181-0300