SH7080 Datasheet, PDF (1607/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
9.5.14 Others
377 Deleted
(2) Access in View of LSI Internal Bus Master
…….
(3) On-Chip Peripheral Module Access
9.5.15 Access to On-Chip FLASH 378
and On-Chip RAM by CPU to
to
9.5.17 Access to External Memory 382
by CPU
Added
Table 10.6 Selecting On-Chip
Peripheral Module Request
Modes with RS3 to RS0 Bits
401
Amended
Transfer
Request
RS3 RS2 RS1 RS0 Source
Transfer
Request
Signal
Source
1 0 1 1 A/D_1 ADI1
ADDR4 to ADDR7
Notes: ADDR4 to ADDR7: A/D data register in A/D
converter channel 1
10.4.6 Operation Timing
419, Added
420
Table 10.9 Number of Cycles per 423
Access to On-Chip RAM by
DMAC
Note added.
Notes: 2. The number of cycles for access to the on-
chip peripheral I/O or an external device are
indicated in section 9.5.16, Access to On-Chip
Peripheral I/O Registers by CPU, and section
9.5.17, Access to External Memory by CPU.
The access cycles are obtained by subtracting
the cycles of Iφ required for L-bus access from
the cycles required for access by the CPU.
Rev. 3.00 May 17, 2007 Page 1549 of 1582
REJ09B0181-0300