SH7080 Datasheet, PDF (21/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2) ................................................................901
18.1 Features.............................................................................................................................. 901
18.2 Input/Output Pins ............................................................................................................... 904
18.3 Register Descriptions ......................................................................................................... 905
18.3.1 I²C Bus Control Register 1 (ICCR1)..................................................................... 905
18.3.2 I²C Bus Control Register 2 (ICCR2)..................................................................... 908
18.3.3 I²C Bus Mode Register (ICMR)............................................................................ 910
18.3.4 I²C Bus Interrupt Enable Register (ICIER) ........................................................... 912
18.3.5 I²C Bus Status Register (ICSR)............................................................................. 914
18.3.6 I²C Bus Slave Address Register (SAR)................................................................. 917
18.3.7 I²C Bus Transmit Data Register (ICDRT)............................................................. 918
18.3.8 I²C Bus Receive Data Register (ICDRR).............................................................. 918
18.3.9 I²C Bus Shift Register (ICDRS)............................................................................ 918
18.3.10 NF2CYC Register (NF2CYC) .............................................................................. 919
18.4 Operation ........................................................................................................................... 920
18.4.1 I²C Bus Format...................................................................................................... 920
18.4.2 Master Transmit Operation ................................................................................... 921
18.4.3 Master Receive Operation..................................................................................... 923
18.4.4 Slave Transmit Operation ..................................................................................... 926
18.4.5 Slave Receive Operation....................................................................................... 929
18.4.6 Clock Synchronous Serial Format ........................................................................ 930
18.4.7 Noise Filter ........................................................................................................... 934
18.4.8 Example of Use..................................................................................................... 935
18.5 I²C2 Interrupt Sources........................................................................................................ 939
18.6 Operation Using the DTC .................................................................................................. 940
18.7 Bit Synchronous Circuit..................................................................................................... 941
18.8 Usage Note......................................................................................................................... 943
18.8.1 Module Standby Mode Setting ............................................................................. 943
18.8.2 Issuance of Stop Condition and Repeated Start Condition ................................... 943
18.8.3 Issuance of a Start Condition and Stop Condition in Sequence ............................ 943
18.8.4 Settings for Multi-Master Operation..................................................................... 944
18.8.5 Reading ICDRR in Master Receive Mode............................................................ 944
Section 19 A/D Converter (ADC)......................................................................945
19.1 Features.............................................................................................................................. 945
19.2 Input/Output Pins ............................................................................................................... 947
19.3 Register Descriptions ......................................................................................................... 948
19.3.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) .............................................. 949
19.3.2 A/D Control/Status Registers_0 to _2 (ADCSR_0 to ADCSR_2)........................ 950
19.3.3 A/D Control Registers_0 to _2 (ADCR_0 to ADCR_2)....................................... 953
Rev. 3.00 May 17, 2007 Page xxi of lviii