SH7080 Datasheet, PDF (1502/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 28 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Td1
Td2
Td3
Td4
Tp
Trw
Tr
Tc1
Tc2
Tc3
Tc4
Tde
t_AD1
t_AD1
Row
address
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
READ command
t_AD1
t_AD1
CSn
RDWR
RASx
CASx
DQMxx
t_CSD
t_RWD
t_RWD
t_RASD
t_RASD
t_RASD
t_RASD
t_CASD
t_DQMD
D31 to D0
t_BSD
BS
t_CSD
t_RWD
t_CASD
t_DQMD
t_RDS2
t_RDH2
t_RDS2
t_RDH2
t_BSD
CKE
TDEANCDKnn^**22
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 28.34 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
CAS Latency 2, WTRCD = 0 Cycle)
Rev. 3.00 May 17, 2007 Page 1444 of 1582
REJ09B0181-0300