SH7080 Datasheet, PDF (473/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
10.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master.
For details, see section 9, Bus State Controller (BSC).
DREQ Pin Sampling Timing: Figures 10.14 to 10.17 show the sample timing of the DREQ input
in each bus mode, respectively.
Determination of DMAC activation by DREQ takes 3 × Bcyc (Bcyc is the external clock (Bφ =
CK) cycle). Timing of the DACK output for the first DREQ acceptance differs depending on the
internal bus state, the AM bit setting in CHCR, and the configuration of the BSC regarding the
transfer source/destination areas, but the fastest case is 6 × Bcyc.
CK
Bus cycle
DREQ
(Rising edge)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non-sensitive period
DMAC
CPU
2nd acceptance
Acceptance started
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Rev. 3.00 May 17, 2007 Page 415 of 1582
REJ09B0181-0300