SH7080 Datasheet, PDF (14/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

9.4.1 Common Control Register (CMNCR) .................................................................. 242
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 8) ..................................... 244
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 8) .................................. 249
9.4.4 SDRAM Control Register (SDCR)....................................................................... 272
9.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 275
9.4.6 Refresh Timer Counter (RTCNT)......................................................................... 277
9.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 278
9.4.8 Bus Function Extending Register (BSCEHR) ...................................................... 279
9.5 Operation ........................................................................................................................... 285
9.5.1 Endian/Access Size and Data Alignment.............................................................. 285
9.5.2 Normal Space Interface ........................................................................................ 288
9.5.3 Access Wait Control ............................................................................................. 294
9.5.4 CSn Assert Period Extension ................................................................................ 296
9.5.5 MPX-I/O Interface................................................................................................ 297
9.5.6 SDRAM Interface ................................................................................................. 301
9.5.7 Burst ROM (Clock Asynchronous) Interface ....................................................... 337
9.5.8 SRAM Interface with Byte Selection ................................................................... 339
9.5.9 PCMCIA Interface................................................................................................ 344
9.5.10 Burst MPX-I/O Interface ...................................................................................... 351
9.5.11 Burst ROM (Clock Synchronous) Interface.......................................................... 356
9.5.12 Wait between Access Cycles ................................................................................ 357
9.5.13 Bus Arbitration ..................................................................................................... 370
9.5.14 Others.................................................................................................................... 376
9.5.15 Access to On-Chip FLASH and On-Chip RAM by CPU ..................................... 378
9.5.16 Access to On-Chip Peripheral I/O Registers by CPU........................................... 378
9.5.17 Access to External Memory by CPU .................................................................... 380
Section 10 Direct Memory Access Controller (DMAC)................................... 383
10.1 Features.............................................................................................................................. 383
10.2 Input/Output Pins............................................................................................................... 385
10.3 Register Descriptions......................................................................................................... 386
10.3.1 DMA Source Address Registers_0 to _3 (SAR_0 to SAR_3) .............................. 387
10.3.2 DMA Destination Address Registers_0 to _3 (DAR_0 to DAR_3) ..................... 388
10.3.3 DMA Transfer Count Registers_0 to _3 (DMATCR_0 to DMATCR_3) ............ 388
10.3.4 DMA Channel Control Registers_0 to _3 (CHCR_0 to CHCR_3) ...................... 389
10.3.5 DMA Operation Register (DMAOR) ................................................................... 394
10.3.6 Bus Function Extending Register (BSCEHR) ...................................................... 396
10.4 Operation ........................................................................................................................... 397
10.4.1 DMA Transfer Flow ............................................................................................. 397
10.4.2 DMA Transfer Requests ....................................................................................... 399
Rev. 3.00 May 17, 2007 Page xiv of lviii