SH7080 Datasheet, PDF (157/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Exception Handling
5.6 Cases when Exceptions are Accepted
When an exception other than resets occurs during decoding the instruction placed in a delay slot
or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in
table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the
exception is accepted.
Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions
Exception
Occurrence Timing
Address
Error
General
Illegal
Slot Illegal Trap
Instruction Instruction Instruction Interrupt
Instruction in delay slot ×*²

×*²

×*³
Immediately after interrupt √
√
√
√
×*⁴
disabled instruction*¹
[Legend]
√:
Accepted
×:
Not accepted
: Does not occur
Notes: 1. Interrupt disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L
2. An exception is accepted before the execution of a delayed branch instruction.
However, when an address error or a slot illegal instruction exception occurs in the
delay slot of the RTE instruction, correct operation is not guaranteed.
3. An exception is accepted after a delayed branch (between instructions in the delay slot
and the branch destination).
4. An exception is accepted after the execution of the next instruction of an interrupt
disabled instruction (before the execution two instructions after an interrupt disabled
instruction).
Rev. 3.00 May 17, 2007 Page 99 of 1582
REJ09B0181-0300