SH7080 Datasheet, PDF (437/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
output to the L bus and the rising edge of Bφ depends on the state of program execution. In the
case shown in the figure, where n = 0 and m = 0, the time required for access is 3 × Iφ + 1 × Bφ +
2 × Pφ.
Iφ
L bus
Bφ
I bus
Pφ
Peripheral bus
(3 + n) × Iφ (1 + m) × Bφ
2 × Pφ
Figure 9.52 Timing of Write Access to On-Chip Peripheral I/O Registers
When Iφ:Bφ:Pφ = 4:2:2
Figure 9.53 shows an example of timing of read access to the peripheral bus when Iφ:Bφ:Pφ =
4:2:1. Transfer from the L bus to the peripheral bus is performed in the same way as for writing. In
the case of reading, however, values output onto the peripheral bus need to be transferred to the
CPU. Although transfers from the peripheral bus to the I bus and from the I bus to the L bus are
performed in synchronization with the rising edge of the respective bus clocks, a period of 2 × Iφ
is actually required because Iφ ≥ Bφ ≥ Pφ. In the case shown in the figure, where n = 0 and m = 1,
the time required for access is 3 × Iφ + 2 × Bφ + 2 × Pφ + 2 × Iφ.
Iφ
L bus
Bφ
I bus
Pφ
Peripheral bus
(3 + n) × Iφ
(1 + m) × Bφ
2 × Pφ
2 × Iφ
Figure 9.53 Timing of Read Access to On-Chip Peripheral I/O Registers
When Iφ:Bφ:Pφ = 4:2:1
Rev. 3.00 May 17, 2007 Page 379 of 1582
REJ09B0181-0300