SH7080 Datasheet, PDF (821/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Serial Communication Interface (SCI)
Receiving Serial Data (Asynchronous Mode):
Figure 15.6 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
Start of reception
[1] Receive error handling and break
detection:
Read ORER, PER, and FER
flags in SCSSR
PER, FER, or ORER = 1?
Yes
No
Error handling
If a receive error occurs, read the ORER,
PER, and FER flags in SCSSR to identify
the error. After performing the
appropriate error processing, ensure that
the ORER, PER, and FER flags are all
cleared to 0. Reception cannot be
resumed if any of these flags are set to 1.
In the case of a framing error, a break
can also be detected by reading the
value of the RXD pin.
Read RDRF flag in SCSSR
No
RDRF = 1?
Yes
Read receive data in
SCRDR, and clear RDRF
flag in SCSSR to 0
No
All data received?
[2] SCI status check and receive data read:
Read SCSSR and check that RDRF = 1,
then read the receive data in SCRDR
clear the RDRF flag to 0.
[3] Serial reception continuation procedure:
To continue serial reception, clear the
RDRF flag to 0 before the stop bit for the
current frame is received. The RDRF flag
is cleared automatically when the direct
memory access controller (DMAC) or
data transfer controller (DTC) is activated
by an RXI interrupt to read the SCRDR
value, and this step is not needed.
Yes
Clear RE bit in SCSCR to 0
End of reception
Figure 15.6 Sample Flowchart for Receiving Serial Data (1)
Rev. 3.00 May 17, 2007 Page 763 of 1582
REJ09B0181-0300