SH7080 Datasheet, PDF (340/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
9
CSSTP3 0
R/W Select Priority for External Memory Access by CPU
Specifies whether or not access to the external space by
the CPU takes priority over DTC or DMAC transfer in
cycle-steal mode.
0: DMAC transfer and DTC transfer have priority.
1: External space access from the CPU has priority.
Note: When this bit is 0, and access to internal I/O from
the CPU is immediately followed by access to
external space from the CPU, a NOP 1Bφ in
duration is inserted between the two access
cycles.
8
DTPR
0
R/W Application of Priority in DTC Activation
When multiple DTC activation requests are generated
before the DTC is activated, specify whether transfer
starts from the first request to have been generated or is
in accord with the priority order for DTC activation
requests.
However, when multiple DTC activation requests have
been issued while the DTC is active, the next transfer to
be triggered will be that with the highest DTC activation
priority.
0: Start transfer in response to the first request to have
been generated.
1: Start transfer in accord with DTC activation request
priority.
Notes: When this bit is set to 1, the following restrictions
apply.
1. The vector information must be in on-chip ROM
or on-chip RAM.
2. The transfer information must be in on-chip
RAM.
3. Skipping of transfer information reading is
always disabled.
7 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 282 of 1582
REJ09B0181-0300