SH7080 Datasheet, PDF (1521/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 28 Electrical Characteristics
28.3.10 Serial Communication Interface with FIFO (SCIF) Timing
Table 28.15 Serial Communication Interface with FIFO (SCIF) Timing
Conditions: V_CC = 3.0 V to 3.6 V or 4.5 V to 5.5 V, AV_CC = 4.5 V to 5.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +85°C (consumer applications),
T_a = –40°C to +85°C (industrial applications)
Item
Symbol Min.
Max.
Input clock cycle (asynchronous)
t_scyc
Input clock cycle (clock synchronous)
t_scyc
Input clock pulse width
t_sckw
Input clock rise time
t_sckr
Input clock fall time
t_sckf
Transmit data delay time
Asynchronous t_TXD
Receive data setup time
t_RXS
Receive data hold time
t_RXH
Transmit data delay time
Receive data setup time
Clock
t_TXD
synchronous
t_RXS
Receive data hold time
t_RXH
RTS delay time
Asynchronous t_RTSD
CTS setup time
t_CTSS
CTS hold time
t_CTSH
Note: t indicates the peripheral clock (Pφ) cycle.
pcyc
4

6

0.4
0.6

1.5

1.5

4 t_pcyc + 10
4 t_pcyc

4 t_pcyc


3 t_pcyc + 10
2 t_pcyc + 50 
2 t_pcyc


4 t_pcyc + 10
4 t_pcyc

4 t_pcyc

Unit
t_pcyc
t_pcyc
t_scyc
t_pcyc
t_pcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reference
Figure
Figure
28.53
Figure
28.54
SCK3
t_sckw
V_IH
V_IH
V_IL
t_sckr
V_IH
V_IL
t_scyc
t_sckf
V_IH
V_IL
Figure 28.53 Input Clock Timing
Rev. 3.00 May 17, 2007 Page 1463 of 1582
REJ09B0181-0300