SH7080 Datasheet, PDF (206/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.3.10 Break Bus Cycle Register B (BBRB)
BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L
bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size
in the break conditions of channel B.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
- CPB2* CPB1* CPB0* CDB1* CDB0 IDB1* IDB0 RWB1* RWB0 SZB1* SZB0*
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These bits are reserved in the mask ROM and ROM-less versions. These bits are always read as 0.
The write value should always be 0.
Initial
Bit
Bit Name Value R/W Description
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10
CPB2*
0
R/W Bus Master Select B for I Bus
9
CPB1*
0
R/W Select the bus master when the I bus is selected as
8
CPB0*
0
R/W ^{the bus cycle of the channel B break condition.}
However, when the L bus is selected as the bus cycle,
the setting of the CPB2 to CPB0 bits is disabled.
000: Condition comparison is not performed
xx1: The CPU cycle is included in the break condition
x1x: The DMAC cycle is included in the break condition
1xx: The DTC cycle is included in the break condition
7
CDB1*
0
R/W L Bus Cycle/I Bus Cycle Select B
6
CDB0
0
R/W Select the L bus cycle or I bus cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Rev. 3.00 May 17, 2007 Page 148 of 1582
REJ09B0181-0300