SH7080 Datasheet, PDF (421/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.32 Minimum Number of Idle Cycles between Access Cycles of CPU, the DMAC
Dual Address Mode, and DTC for the SDRAM Interface
BSC Register Setting
CSnBCR CS3WCR. CS3WCR.
Idle
WTRP TRWL Read to
Setting Setting Setting Read
0
1
0
1/1/1/1
0
1
1
1/1/1/1
0
1
2
1/1/1/1
0
1
3
1/1/1/1
0
2
0
2/2/2/2
0
2
1
2/2/2/2
0
2
2
2/2/2/2
0
2
3
2/2/2/2
0
3
0
3/3/3/3
0
3
1
3/3/3/3
0
3
2
3/3/3/3
0
3
3
3/3/3/3
0
4
0
4/4/4/4
0
4
1
4/4/4/4
0
4
2
4/4/4/4
0
4
3
4/4/4/4
1
1
0
2/2/2/2
1
1
1
2/2/2/2
1
1
2
2/2/2/2
1
1
3
2/2/2/2
1
2
0
2/2/2/2
1
2
1
2/2/2/2
1
2
2
2/2/2/2
1
2
3
2/2/2/2
1
3
0
3/3/3/3
1
3
1
3/3/3/3
CPU Access
Write to
Write
0/0/0/0
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
4/4/4/4
5/5/5/5
3/3/3/3
4/4/4/4
5/5/5/5
6/6/6/6
1/1/1/1
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
Read to
Write
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
4/4/4/4
4/4/4/4
4/4/4/4
4/4/4/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
3/3/3/4
Write to
Read
0/0/0/0
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
4/4/4/4
5/5/5/5
3/3/3/3
4/4/4/4
5/5/5/5
6/6/6/6
1/1/1/1
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
DMAC or DTC
Access
Read to Write to
Write Read
2
0
2
1
2
2
2
3
2
1
2
2
2
3
2
4
3
2
3
3
3
4
3
5
4
3
4
4
4
5
4
6
2
1
2
1
2
2
2
3
2
1
2
2
2
3
2
4
3
2
3
3
Rev. 3.00 May 17, 2007 Page 363 of 1582
REJ09B0181-0300