SH7080 Datasheet, PDF (451/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
1
TE
0
R/(W)* Transfer End Flag
Shows that DMA transfer ends. The TE bit is set to 1
when data transfer ends when DMATCR becomes to 0.
The TE bit is not set to 1 in the following cases.
• DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR is cleared to 0.
• DMA transfer is ended by clearing the DE bit and
DME bit in the DMA operation register (DMAOR).
To clear the TE bit, the TE bit should be written to 0 after
reading 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
interrupted
[Clearing condition]
Writing 0 after TE = 1 read
1: DMA transfer ends by the specified count (DMATCR =
0)
0
DE
0
R/W DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and DME
bit in DMAOR to 1. In this time, all of the bits TE, NMIF,
and AE in DMAOR must be 0. In an external request or
peripheral module request, DMA transfer starts if DMA
transfer request is generated by the devices or peripheral
modules after setting the bits DE and DME to 1. In this
case, however, all of the bits TE, NMIF, and AE must be
0, which is the same as in the case of auto request mode.
Clearing the DE bit to 0 can terminate the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 3.00 May 17, 2007 Page 393 of 1582
REJ09B0181-0300