SH7080 Datasheet, PDF (669/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MPφ
External
clock
TCNT input
clock
Rising edge
Falling edge
TCNT
N-1
N
N-1
Figure 11.96 Count Timing in External Clock Operation (Phase Counting Mode)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match
signal is not generated until the TCNT input clock is generated.
Figure 11.97 shows output compare output timing (normal mode and PWM mode) and figure
11.98 shows output compare output timing (complementary PWM mode and reset synchronous
PWM mode).
MPφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TIOC pin
Figure 11.97 Output Compare Output Timing (Normal Mode/PWM Mode)
Rev. 3.00 May 17, 2007 Page 611 of 1582
REJ09B0181-0300