SH7080 Datasheet, PDF (242/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.3 Activation Sources
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.
8.4 Location of Transfer Information and DTC Vector Table
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information located in the data area is shown in figure 8.2.
Only in the case where all transfer sources/transfer destinations are in on-chip RAM and on-chip
peripheral modules, short address mode can be selected by setting the DTSA bit in the bus
function extending register (BSCEHR) to 1 (see section 9.4.8, Bus Function Extending Register
(BSCEHR)).
Normally, four longwords of transfer information has to be read. But if short address mode is
selected, the size of transfer information is reduced to three longwords, which can shorten the
period over which the DTC is active.
The DTC reads the start address of the transfer information from the vector table for every
activation source and reads the transfer information from this start address. Figure 8.3 shows
correspondences between the DTC vector table and transfer information.
Rev. 3.00 May 17, 2007 Page 184 of 1582
REJ09B0181-0300