SH7080 Datasheet, PDF (34/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Figure 11.60 Example of Synchronous Clearing in Dead Time during Down-Counting
(Timing (8) in Figure 11.56; Bit WRE of TWCR is 1) ......................................... 573
Figure 11.61 Example of Synchronous Clearing in Interval Tb at Trough
(Timing (11) in Figure 11.56; Bit WRE of TWCR is 1) ....................................... 574
Figure 11.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified
by SCC Bit in TWCR ............................................................................................ 575
Figure 11.63 Example of Procedure for Suppressing MTU2–MTU2S Synchronous
Counter Clearing ................................................................................................... 576
Figure 11.64 Example of Synchronous Clearing in Dead Time during Up-Counting
(Timing (3) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of
MTU2S)................................................................................................................. 577
Figure 11.65 Example of Synchronous Clearing in Interval Tb at Crest
(Timing (6) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR
of MTU2S) ............................................................................................................ 578
Figure 11.66 Example of Synchronous Clearing in Dead Time during Down-Counting
(Timing (8) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR
of MTU2S) ............................................................................................................ 579
Figure 11.67 Example of Synchronous Clearing in Interval Tb at Trough
(Timing (11) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of
MTU2S)................................................................................................................. 580
Figure 11.68 Example of Counter Clearing Operation by TGRA_3 Compare Match................ 581
Figure 11.69 Example of Output Phase Switching by External Input (1)................................... 582
Figure 11.70 Example of Output Phase Switching by External Input (2)................................... 583
Figure 11.71 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1).. 583
Figure 11.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2).. 584
Figure 11.73 Example of Interrupt Skipping Operation Setting Procedure................................ 585
Figure 11.74 Periods during which Interrupt Skipping Count can be Changed ......................... 586
Figure 11.75 Example of Interrupt Skipping Operation ............................................................. 586
Figure 11.76 Example of Operation when Buffer Transfer is Suppressed
(BTE1 = 0 and BTE0 = 1) ..................................................................................... 588
Figure 11.77 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping
(BTE1 = 1 and BTE0 = 0) ..................................................................................... 589
Figure 11.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-
Enabled Period....................................................................................................... 589
Figure 11.79 Example of Procedure for Specifying A/D Converter Start Request Delaying
Function................................................................................................................. 591
Figure 11.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation .... 592
Figure 11.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked
with Interrupt Skipping.......................................................................................... 593
Rev. 3.00 May 17, 2007 Page xxxiv of Iviii