SH7080 Datasheet, PDF (1394/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 26 Power-Down Modes
26.3.6 Standby Control Register 6 (STBCR6)
STBCR6 is an 8-bit readable/writable register that specifies the state of the power-down modes.
Bit: 7
6
5
4
3
2
1
0
AUD
SRST
HIZ
-
-
-
-
STBY
MD
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R R/W R
Bit
7
6
5 to 2
1
0
Bit Name
AUDSRST
Initial
Value
0
HIZ
0

All 0
STBYMD 0

0
R/W Description
R/W AUD Software Reset
This bit controls the AUD reset by software. When 0 is
written to AUDSRST, the AUD module shifts to the
power-on reset state.
0: Shifts to the AUD reset state
1: Clears the AUD reset
When setting this bit to 1, the MSTP25 bit in STBCR5
should be 0.
R/W Port High-Impedance
In software standby mode, this bit selects whether the
pin state is retained or changed to high-impedance.
0: In software standby mode, the pin state is retained
1: In software standby mode, the pin state is changed
to high-impedance
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Software Standby Mode Select
This bit selects a transition to software standby mode or
deep software standby mode by executing the SLEEP
instruction when the STBY bit is 1 in STBCR1.
0: Transition to deep software standby mode
1: Transition to software standby mode
R Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 1336 of 1582
REJ09B0181-0300