SH7080 Datasheet, PDF (436/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.15 Access to On-Chip FLASH and On-Chip RAM by CPU
Access to the on-chip FLASH for read is synchronized with Iφ clock and is executed in one clock
cycle. For details on programming and erasing, see section 23, Flash Memory.
Access to the on-chip RAM for read/write is synchronized with I φ clock and is executed in one
clock cycle. For details, see section 25, RAM.
9.5.16 Access to On-Chip Peripheral I/O Registers by CPU
Table 9.35 shows the number of cycles required for access to the on-chip peripheral I/O registers
by the CPU.
Table 9.35 Number of Cycles for Access to On-Chip Peripheral I/O Registers
Number of Access Cycles
Write
(3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ
Read
(3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ + 2 × Iφ
Notes: 1. When Iφ:Bφ = 8:1, n = 0 to 7.
When Iφ:Bφ = 4:1, n = 0 to 3.
When Bφ:Pφ = 4:1, m = 0 to 3.
When Iφ:Bφ = 3:1, n = 0 to 2.
When Bφ:Pφ = 3:1, m = 0 to 2.
When Iφ:Bφ = 2:1, n = 0 to 1.
When Bφ:Pφ = 2:1, m = 0 to 1.
When Iφ:Bφ = 1:1, n = 0.
When Bφ:Pφ = 1:1, m = 0.
n and m depend on the internal execution state.
2. The clock ratio of MIφ and MPφ does not affect the number of access cycles.
Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus
are input and output in synchronization with rising edges of the corresponding clock signal. The L
bus, I bus, and peripheral bus are synchronized with the Iφ, Bφ, and Pφ clock, respectively. Figure
9.52 shows an example of the timing of write access to a register in 2Pφ cycle access with the
connected peripheral bus width of 16 bits when Iφ:Bφ:Pφ = 4:2:2. In access to the on-chip
peripheral I/O registers, the CPU requires three cycles of Iφ for preparation of data transfer to the I
bus after the data has been output to the L bus. After these three cycles, data can be transferred to
the I bus in synchronization with rising edges of Bφ. However, as there are two Iφ clock cycles in
a single Bφ clock cycle when Iφ: Bφ = 4:2, transfer of data from the L bus to the I bus takes (3 +
n) × Iφ (n = 0 to 1) (3 × Iφ is indicated in figure 9.52). The relation between the timing of data
Rev. 3.00 May 17, 2007 Page 378 of 1582
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