SH7080 Datasheet, PDF (230/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
INTC
On-chip
memory
On-chip
peripheral
module
Interrupt
request
CPU interrupt
request
Interrupt source
clear request
DTC
Register
control
Activation
control
CPU/DTC
/DMAC
request
determination
Interrupt
control
MRA
MRB
SAR
DAR
CRA
CRB
DTCERA to
DTCERE
DTCCR
DTCVBR
External
memory
Bus interface
External device
(memory mapped)
Bus state
controller
DMAC
CHCR[11:8]
DMAC activation source clear signal
[Legend]
MRA, MRB:
DTC mode registers A, B
SAR:
DTC source address register
DAR:
DTC destination address register
CRA, CRB:
DTC transfer count registers A, B
DTCERA to DTCERE: DTC enable registers A to E
DTCCR:
DTC control register
DTCVBR:
DTC vector base register
CHCR:
DMA channel control register
Figure 8.1 Block Diagram of DTC
Rev. 3.00 May 17, 2007 Page 172 of 1582
REJ09B0181-0300