SH7080 Datasheet, PDF (858/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
4
RE
0
R/W Receive Enable
Enables or disables the SCIF serial receiver.
0:Receiver disabled*¹
1: Receiver enabled*²
Note: 1. Clearing RE to 0 does not affect the receive
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
2. Serial reception starts when a start bit is
detected in asynchronous mode, or
synchronous clock input is detected in clock
synchronous mode. Select the receive format
in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
3
REIE
0
R/W Receive Error Interrupt Enable
Enables or disables the receive-error (ERIF) interrupts
and break (BRIF) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERIF) and break interrupt
(BRIF) requests are disabled*
1: Receive-error interrupt (ERIF) and break interrupt
(BRIF) requests are enabled
Note: * ERIF or BRIF interrupt requests can be cleared
by reading the ER, BR or ORER flag after it
has been set to 1, then clearing the flag to 0, or
by clearing RIE and REIE to 0. Even if RIE is
set to 0, when REIE is set to 1, ERIF or BRIF
interrupt requests are enabled.
Rev. 3.00 May 17, 2007 Page 800 of 1582
REJ09B0181-0300