SH7080 Datasheet, PDF (1497/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 28 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Tr
Trw
Trw
Tc1
Trwl
t_AD1
Row address
t_AD1
t_AD1
t_AD1
Column
address
t_AD1
t_AD1
WRITA
command
CSn
RDWR
RASx
CASx
DQMxx
t_CSD
t_RWD
t_RASD
t_RASD
t_DQMD
D31 to D0
BS
t_RWD
t_CSD
t_RWD
t_CASD
t_CASD
t_DQMD
t_WDD2
t_WDH2
t_BSD
t_BSD
CKE
DACKn^*2
TENDn^*2
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 28.29 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)
Rev. 3.00 May 17, 2007 Page 1439 of 1582
REJ09B0181-0300