SH7080 Datasheet, PDF (125/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a bus clock (Bφ),
a peripheral clock (Pφ), and clocks (MIφ and MPφ) for the MTU2S and MTU2 modules. The CPG
also controls power-down modes.
4.1 Features
• Five clocks generated independently
An internal clock (Iφ) for the CPU; a peripheral clock (Pφ) for the on-chip peripheral modules;
a bus clock (Bφ = CK) for the external bus interface; a MTU2S clock (MIφ) for the on-chip
MTU2S module; and a MTU2 clock (MPφ) for the on-chip MTU2 module.
• Frequency change function
Frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock
(MIφ), and MTU2 clock (MPφ) can be changed independently using the divider circuit within
the CPG. Frequencies are changed by software using the frequency control register (FRQCR)
setting.
• Power-down mode control
The clock can be stopped in sleep mode and standby mode and specific modules can be
stopped using the module standby function.
• Oscillation stop detection
If the clock supplied through the clock input pin stops for any reason, the timer pins can be
automatically placed in the high-impedance state.
CPGS301C_000020030900
Rev. 3.00 May 17, 2007 Page 67 of 1582
REJ09B0181-0300