SH7080 Datasheet, PDF (476/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
When 16-byte transfer to an external device is performed, when 8-bit or 16-bit external device is
accessed in longword units, or when an 8-bit external device is accessed in word units, each DMA
transfer unit is divided into multiple bus cycles. If negation of CS between bus cycles is specified
in these cases, the DACK and TEND outputs are also divided for data alignment. This example is
illustrated in figure 10.19.
With divided DACK, sampling of DREQ is not detected correctly and a maximum of one extra
overrun may occur. To avoid this, use the settings with which DACK is not divided, or in the case
when DACK is divided, specify the transfer size that is smaller than the bus width of the external
device.
CK
Address
CS
RD
T1 T2 Taw T1 T2
Data
WRxx
DACKn
(Active-low)
TENDn
(Active-low)
WAIT
Note: The DACK and TEND are asserted for the last transfer unit
of the DMA transfer. When the transfer unit is divided into
several bus cycles and the CS is negated between bus cycles,
the DACK and TEND are also divided.
Figure 10.19 BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 3.00 May 17, 2007 Page 418 of 1582
REJ09B0181-0300