SH7080 Datasheet, PDF (73/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Classification Symbol
Bus control
CS8 to CS0
RD
RDWR
BS
AH
FRAME
WRHH
WRHL
WRH
WRL
WAIT
Section 1 Overview
I/O Name
Function
O Chip select 8 to 0 Chip-select signal for external
memory or devices.
CS7, CS3, and CS0 are available in
the SH7083.
CS7 to CS0 are available in the
SH7084/SH7085.
O Read
Indicates reading of data from
external devices.
O Read/write
Read/write signal
O Bus start
Bus-cycle start
O Address hold
Address hold timing signal for the
device that uses the address/data-
multiplexed bus.
Available only in the
SH7084/SH7085/SH7086.
O FRAME signal In burst MPX-I/O interface mode,
negated before the last bus cycle to
indicate that the next bus cycle is the
last access.
Available only in the
SH7085/SH7086.
O Write to HH byte Indicates a write access to bits 31 to
24 of the external data.
Available only in the
SH7085/SH7086.
O Write to HL byte Indicates a write access to bits 23 to
16 of the external data.
Available only in the
SH7085/SH7086.
O Write to upper Indicates a write access to bits 15 to
byte
8 of the external data.
O Write to lower Indicates a write access to bits 7 to 0
byte
of the external data.
I
Wait
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
Rev. 3.00 May 17, 2007 Page 15 of 1582
REJ09B0181-0300