SH7080 Datasheet, PDF (278/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.2 Input/Output Pins
The pin configuration of the BSC is listed in table 9.1.
Table 9.1 Pin Configuration
Name
A29 to A0
D31 to D0
BS
CS0 to CS8
CE1A
CE2A
CE1B
CE2B
RDWR
RD
WRHH
WRHL
WRH
WRL
I/O
Function
Output Address bus
I/O
Data bus
Output Bus cycle start
Asserted when a normal space, burst ROM (clock synchronous or
asynchronous), MPX-I/O, burst MPX-I/O, or PCMCIA is accessed.
When SDRAM is accessed, this signal is asserted at the same
timing as CAS.
Output Chip select
Output Chip enable for PCMCIA connected to area 5
Output Chip enable for PCMCIA connected to area 5
Output Chip enable for PCMCIA connected to area 6
Output Chip enable for PCMCIA connected to area 6
Output Read/write
Connected to WE pin when SDRAM or SRAM with byte selection is
used.
Output Read pulse signal (read data output enable signal)
Strobe signal for indicating memory read cycles when PCMCIA is
used.
Output Indicates byte write through D31 to D24.
Connected to the byte select pin when SRAM with byte selection is
used.
Output Indicates byte write through D23 to D16.
Connected to the byte select pin when SRAM with byte selection is
used.
Output Indicates byte write through D15 to D8.
Connected to the byte select pin when SRAM with byte selection is
used.
Output Indicates byte write through D7 to D0.
Connected to the byte select pin when SRAM with byte selection is
used.
Rev. 3.00 May 17, 2007 Page 220 of 1582
REJ09B0181-0300