SH7080 Datasheet, PDF (275/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. BSC functions enable this LSI to
connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1 Features
1. External address space
• A maximum 64 Mbytes for each of eight areas, CS0 to CS7, and a maximum 1 Gbyte for the
CS8 area
• Can specify the normal space interface, SRAM interface with byte selection, burst ROM
(clock synchronous or asynchronous), MPX-I/O, burst MPX-I/O, SDRAM, or PCMCIA for
each address space
• Can select the data bus width (8, 16, or 32 bits) for each address space
• Controls the insertion of the wait state for each address space.
• Controls the insertion of the wait state for each read access and write access
• Can set the independent idling cycle in the continuous access for five cases: read-write (in
same space/different space), read-read (in same space/different space), the first cycle is a write
access.
2. Normal space interface
• Supports the interface that can directly connect to the SRAM
3. Burst ROM interface (clock asynchronous)
• High-speed access to the ROM that has the page mode function
4. MPX-I/O interface
• Directly connects peripheral LSIs with address/data multiplexing
5. SDRAM interface
• Can set the SDRAM up to 2 areas
• Multiplex output for row address/column address
• Efficient access by single read/single write
• High-speed access by bank-active mode
• Supports an auto-refresh and self-refresh
6. SRAM interface with byte selection
• Supports interfaces that can be connected directly to SRAM with byte selection
Rev. 3.00 May 17, 2007 Page 217 of 1582
REJ09B0181-0300