SH7080 Datasheet, PDF (450/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
5
TB
0
R/W Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
Note: When performing DMA transfer in burst mode with
MTU2 activation request, set the corresponding bit
among DMMTU4 to DMMTU0 in bus function
extending register (BSCEHR) (see section 9.4.8,
Bus Function Extending Register (BSCEHR)).
4, 3 TS[1:0] 00
R/W Transfer Size 1, 0
Specify the size of data to be transferred.
Select the size of data to be transferred when the source
or destination is an on-chip peripheral module register of
which transfer size is specified.
00: Byte size
01: Word size (2 bytes)
10: Longword size (4 bytes)
11: 16-byte unit (four longword transfers)
2
IE
0
R/W Interrupt Enable
Specifies whether or not an interrupt request is generated
to the CPU at the end of the DMA transfer. Setting this bit
to 1 generates an interrupt request (DEI) to the CPU
when the TE bit is set to 1.
0: Interrupt request is disabled.
1: Interrupt request is enabled.
Rev. 3.00 May 17, 2007 Page 392 of 1582
REJ09B0181-0300