SH7080 Datasheet, PDF (535/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
0
TTSA
0
R/W Timing Select A
Specifies the timing for transferring data from TGRC to
TGRA in each channel when they are used together for
buffer operation. When using a channel in other than
PWM mode, do not set this bit to 1.
0: When compare match A occurs in each channel
1: When TCNT is cleared in each channel
11.3.8 Timer Input Capture Control Register (TICCR)
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1
and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
I2BE I2AE I1BE I1AE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 4 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
I2BE
0
R/W Input Capture Enable
Specifies whether to include the TIOC2B pin in the
TGRB_1 input capture conditions.
0: Does not include the TIOC2B pin in the TGRB_1
input capture conditions
1: Includes the TIOC2B pin in the TGRB_1 input
capture conditions
Rev. 3.00 May 17, 2007 Page 477 of 1582
REJ09B0181-0300