SH7080 Datasheet, PDF (1610/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
Figure 11.88 Example of External 601
Pulse Width Measurement
(Measuring High Pulse Width)
Amended
MPφ
TIC5U
TCNT5_U
0000
0001 0002 0003 0004 0005 0006 0007
0007 0008 0009 000A 000B
11.7.22 Simultaneous Capture of 638
TCNT_1 and TCNT_2 in Cascade
Connection
Table 13.5 Interrupt Sources and 710
Conditions
Added
….In this case, the values of TCNT_1 = H'FFF1 and
TCNT_2 = H'0000 should be transferred to TGRA_1
and TGRA_2 or to TGRB_1 and TGRB_2, but the
values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are
erroneously transferred.
The MTU2 has a new function that allows simultaneous
capture of TCNT_1 and TCNT_2 with a single input-
capture input as the trigger. This function allows reading
of the 32-bit counter such that TCNT_1 and TCNT_2
are captured at the same time. For details, see section,
11.3.8, Timer Input Capture Control Register (TICCR).
Amended
Name
Interrupt Source
OEI3
Output enable interrupt 3
OEI2
Output enable interrupt 2
13.6 Usage Note
Figure 14.3 Operation in
Watchdog Timer Mode
(When WTCNT Count Clock is
Specified to Pφ/32 by CKS2 to
CKS0)
711 Added
721 Amended
Internal reset signal
(power-on reset selected)
Internal reset signal
(manual reset selected)
3 Pφ + one cycle of count clock
18 Pφ clock
Rev. 3.00 May 17, 2007 Page 1552 of 1582
REJ09B0181-0300