SH7080 Datasheet, PDF (856/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit
15 to 8
Bit Name

7
TIE
Initial
value
All 0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXIF).
Serial transmit data in the transmit FIFO data register
(SCFTDR) is send to the transmit shift register
(SCTSR). Then, the TDFE flag in the serial status
register (SCFSR) is set to1 when the number of data in
SCFTDR becomes less than the number of
transmission triggers. At this time, a TXIF is requested.
0: Transmit-FIFO-data-empty interrupt request (TXIF) is
disabled*
1: Transmit-FIFO-data-empty interrupt request (TXIF) is
enabled
Note: * The TXIF interrupt request can be cleared by
writing a greater number of transmit data than
the specified transmission trigger number to
SCFTDR and by clearing the TDFE bit to 0
after reading 1 from the TDFE bit, or can be
cleared by clearing this bit to 0.
Rev. 3.00 May 17, 2007 Page 798 of 1582
REJ09B0181-0300