SH7080 Datasheet, PDF (527/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
4
TCFV
0
R/(W)*¹ Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
• When the TCNT value overflows (changes from
H'FFFF to H'0000)
In channel 4, when the TCNT_4 value underflows
(changes from H'0001 to H'0000) in complementary
PWM mode, this flag is also set.
[Clearing condition]
3
TGFD
0
• When 0 is written to TCFV after reading TCFV = 1*²
In cannel 4, when DTC is activated by TCIV interrupt
and the DISEL bit of MRB in DTC is 0, this flag is
also cleared.
R/(W)*¹ Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0, 3, and 4. Only
0 can be written, for flag clearing. In channels 1 and 2,
bit 3 is reserved. It is always read as 0 and the write
value should always be 0.
[Setting conditions]
• When TCNT = TGRD and TGRD is functioning as
output compare register
• When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
[Clearing conditions]
• When DTC is activated by TGID interrupt and the
DISEL bit of MRB in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1*²
Rev. 3.00 May 17, 2007 Page 469 of 1582
REJ09B0181-0300