SH7080 Datasheet, PDF (1000/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Table 18.6 Time for Monitoring SCL
CKS3
CKS2
NF2CYC
Time for Monitoring SCL*¹
0
0
0
6.5
t *2
pcyc
1
5.5
t *2
pcyc
1
0
18.5
t *2
pcyc
1
17.5
t *2
pcyc
1
0
0
16.5
t *2
pcyc
1
15.5
t *2
pcyc
1
0
40.5
t *2
pcyc
1
39.5
t *2
pcyc
Notes: 1. SCL pin level is monitored after "time for monitoring SCL" has elapsed from the rising
edge of the reference clock for monitoring SCL.
2. t_pcyc indicates the period of the peripheral clock.
Rev. 3.00 May 17, 2007 Page 942 of 1582
REJ09B0181-0300