SH7080 Datasheet, PDF (1601/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
7.3.3 Break Bus Cycle Register A 140, Amended
(BBRA)
141 _{Bit Bit Name Description}
10 CPA2* Bus Master Select A for I Bus
9 CPA1*
8 CPA0*
7 CDA1* L Bus Cycle/I Bus Cycle Select A
6 CDA0
5 IDA1*
4 IDA0
Instruction Fetch/Data Access
Select A
3 RWA1* Read/Write Select A
2 RWA0
1 SZA1*
Operand Size Select A
0 SZA0*
Note: * These bits are reserved in the mask ROM and
ROM-less versions. These bits are always read
as 0. The write value should always be 0.
7.3.4 Break Data Register A
142,
(BDRA) (Only in F-ZTAT Version) 143,
7.3.5 Break Data Mask Register A ^146,
(BDMRA) (Only in F-ZTAT
147,
Version)
155,
156,
7.3.8 Break Data Register B
157
(BDRB) (Only in F-ZTAT Version)
Amended
7.3.9 Break Data Mask Register B
(BDMRB) (Only in F-ZTAT
Version)
7.3.12 Execution Times Break
Register (BETR) (Only in F-ZTAT
Version)
7.3.13 Branch Source Register
(BRSR) (Only in F-ZTAT Version)
7.3.14 Branch Destination
Register (BRDR) (Only in F-ZTAT
Version)
Rev. 3.00 May 17, 2007 Page 1543 of 1582
REJ09B0181-0300