SH7080 Datasheet, PDF (130/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
4.3 Clock Operating Mode
Table 4.3 shows the clock operating mode of this LSI.
Table 4.3 Clock Operating Mode
Clock Operating
Mode
Source
Clock I/O
Output
PLL Circuit
Input to Divider
1
EXTAL input or CK*
ON (×8)
×8
crystal resonator
Note: * To output the clock through the clock output (CK) pin, appropriate settings should be
made in the pin function controller (PFC). For details, refer to section 21, Pin Function
Controller (PFC).
Mode 1: The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the
PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to
generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 5
MHz to 12.5 MHz can be used, the internal clock (Iφ) frequency ranges from 10 MHz to 80 MHz.
Maximum operating frequencies:
Iφ = 80 MHz, Bφ = 40 MHz, Pφ = 40 MHz, MIφ = 80 MHz, and MPφ = 40 MHz
Table 4.4 shows the frequency division ratios that can be specified with FRQCR.
Rev. 3.00 May 17, 2007 Page 72 of 1582
REJ09B0181-0300